Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to\r\nsupport high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in\r\nplace to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all\r\ndesigns run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of\r\npartial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to\r\ndynamically self-adopt the clock frequency during runtime by reconfiguring the Digital ClockManagers.We also present a method\r\nfor online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be\r\nused as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further,\r\nthe tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the\r\ndistributed dynamic frequency scaling method with little additional overhead.
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